Function memory_aarch64::configure_translation_registers

source · 
pub fn configure_translation_registers()
Expand description

Configures paging for Theseus.

Resulting Configuration

  • MAIR slot 0 is for cacheable normal DRAM
  • MAIR slot 1 is for non-cacheable device memory
  • A physical address is 48-bits long
  • Only the first translation unit is used (TTBR0)
  • The Page Size is 4KiB
  • The ASID size is 8 bits.
  • The MMU is allowed to update the DIRTY and ACCESSED flags in a page table entry.